DNP Embedded Module with Xscale and Linux

The DIL/NetPC DNP/2110 is a very compact Intel 400 MHz PXA255 Xscale-based low power embedded controller with TCP/IP stack and web server for high-speed embedded networking applications in a harsh environment. The DIL/NetPC offers the footprint of a standard 64-pin DIL socket with 2.54 mm centers (0.1 inch pin grid) and all the hardware and software features necessary to add high-speed networking capabilities to any product design. The DIL/NetPC was developed specifically for products that need to be connected to 10 or 100 Mbps Ethernet-based TCP/IP networks with minimum development costs.

The DNP/2110 comes as ready-to-run embedded networking system for a operating temperature range from -40°C to +85°C (version with 0 °C to +70 °C also available). The use of the DNP/2110 will allow you to realize a substantial time and costs savings over other chip-based approaches. Currently, there is no other 10/100 Mbps Ethernet- and TCP/IP-based embedded networking solution with more development time savings on the market. There is also no faster Time-to-Market for your product with lower costs if 10/100 Mbps Ethernet, full TCP/IP and a embedded Web server or other TCP/IP-based server software is required.

To interface the DNP/2110 with existing devices and equipment, the DNP/2110 offers two asynchronous serial RS232C interfaces with TTL levels and handshake signals (COM1/COM2 - 16550 compatible), 20-bit general purpose high-speed parallel I/Os and a 8-bit extension bus with interrupt inputs and chip select outputs. There are two ways for DNP/2110 integration: 1. Adapt the DNP/2110 to your existing product. Use the existing I/Os within your product to communicate with the DNP/2110. 2. Use the DNP/2110 to control and monitor the hardware of your existing product. This might enable you to replace your existing controller entirely. In a new product design, the DNP/2110 can be the main controller. Additional I/Os are driven by the 8-bit extension bus.

The on-board FLASH memory provides storage for the DNP/2110 operating system with TCP/IP stack and embedded web server as well as OEM applications and data. The FLASH memory is in-system programmable over JTAG, serial and the Ethernet interface. The boot block of the FLASH memory is only in-system programmable over the JTAG interface through a special cable attached to a PC parallel port. For all other FLASH blocks, you can use also a high-speed serial connection through the DNP/2110 COM1 port or the 10/100 Mbps Ethernet interface for in-system programming. The DNP/2110 in-system programming was developed for OEM application software, operating system downloads (i.e. upgrade from embedded Linux to eCos) and data download and to make it easier to update the on-board FLASH content in the field.

• Intel Xscale PXA255 CPU with 400 MHz Clock Speed
• 480 MIPS Dhrystone 2.1 (depends on compiler type and version)
• 397.31 Linux BogoMIPS at 400 MHz
• 16 MByte or 32 Mbyte 32-bit SDRAM Memory
• 16 MByte FLASH Memory
• 10/100 Mbps Ethernet Interface
• Two 16550 Serial Ports (one with all Handshakes)
• 20-bit General Purpose high-speed Parallel I/O
• 8-bit I/O Expansion Bus
• 5 Interrupt Inputs, 4 Chip Select Outputs
• Programmable Watchdog Timer
• JTAG IEEE 1149.1 Test Interface
• In-System Programming Features
• 64-pin JEDEC DIL-64 Connector, 2.54 mm Centers
• 3.3 Volt Low Power Design, Supply Voltage 3.3 VDC (+- 5%)
• Supply Current 350 mA typ. at 400 MHz
• -40°C to +85°C Operating Temperature (version with 0°C to +70°C also available)
• Size 82 mm * 28 mm

The DNP/2110 is build around the Intel Xscale PXA255 32-bit RISC microcontroller running with 400 MHz. The PXA255 has a large instruction cache (I-Cache) and data cache (D-Cache), memory-management unit (MMU), and read/write buffers. The PXA255 offers high-performance processing power with up to 480 Dhrystone 2.1 MIPS. The PXA255 CPU core implements the ARM 5TE architecture as defined in the ARM Architecture Reference Manual with 32-bit ARM and 16-bit Thumb instruction set. The PXA255 provides a complete set of internal peripherals. There are multiple serial communication channels, general-purpose I/O ports, timers, interrupt control, reset control, and power management functions.

The external main components around the Intel Xscale PXA255 32-bit RISC microcontroller on the DNP/2110 are one FLASH chip with 16 MBytes, one 16 or 32 MByte SDRAM chip, and one 10/100 Mbps Ethernet LAN controller with 10BASE-T and 100BASE-TX physical layer interface. The FLASH stores the hardware setup code, the U-Boot boot loader, operating system, and OEM applications. The 32-bit SDRAM access and the refresh operation is driven by the PXA255 integrated SDRAM controller.

The DNP/2110 10/100 Mbps Ethernet controller is a SMSC LAN91C111 single chip MAC+PHY. This highly-integrated Ethernet LAN controller includes 8 KByte internal memory for receive and transmit FIFO buffers, an IEEE 802.3/802.3u Ethernet MAC engine, and internal 10BASE-T and 100BASE-TX transmit and receive filters. The SMSC LAN91C111 supports full-duplex switched Ethernet operations and auto negotiation for 10 and 100 Mbps. For the DNP/2110 LAN integration, the PHY interface needs only an external low-cost isolation transformer.

The mechanical interface between the DNP/2110 and existing devices and equipment is a JEDEC 64-pin DIL connector with 2.54 mm centers. This allows the direct integration to a standard 64-pin DIL socket. The 64 pins in total are used for 3.3 volt power supply (2 pins), Reset in and out (2 pins), two serial interfaces (10 pins), 10/100 Mbps Ethernet interface (4 pins), general purpose parallel I/O (20 pins) and the extension bus (26 pins).